R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 989

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 0 – Reset/Halt/Sleep Interrupt Flag (IRR0): This flag can get set for three different reasons.
It can indicate that:
1. Reset mode has been entered after a SW (MCR0) or HW reset
2. Halt mode has been entered after a Halt request (MCR1)
3. Sleep mode has been entered after a sleep request (MCR5) has been made while in Halt mode.
The GSR may be read after this bit is set to determine which state RCAN-TL1 is in.
Important: When a Sleep mode request needs to be made, the Halt mode must be used
beforehand. Please refer to the MCR5 description and Figure 19.15 Halt Mode/Sleep Mode.
IRR0 is set by the transition from "0" to "1" of GSR3 or GSR4 or by transition from Halt mode to
Sleep mode. So, IRR0 is not set if RCAN-TL1 enters Halt mode again right after exiting from Halt
mode, without GSR4 being cleared. Similarly, IRR0 is not set by direct transition from Sleep
mode to Halt Request. At the transition from Halt/Sleep mode to Transition/Reception, clearing
GSR4 needs (one-bit time - TSEG2) to (one-bit time * 2 - TSEG2).
In the case of Reset mode, IRR0 is set, however, the interrupt to the CPU is not asserted since
IMR0 is automatically set by initialisation.
Bit 1: IRR1
0
1
Bit 0: IRR0
0
1
Description
[Clearing condition] Clearing of all bits in RXPR (Initial value)
Data frame received and stored in Mailbox
[Setting condition] When data is received and the corresponding MBIMR = 0
Description
[Clearing condition] Writing 1
Transition to S/W reset mode or transition to halt mode or transition to sleep
mode (Initial value)
[Setting condition]
When reset/halt/sleep transition is completed after a reset (MCR0 or HW) or
Halt mode (MCR1) or Sleep mode (MCR5) is requested
Section 19 Controller Area Network (RCAN-TL1)
Rev. 3.00 Sep. 28, 2009 Page 957 of 1650
REJ09B0313-0300