R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1101

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

22.3.6
FLDTCNTR is a 32-bit readable/writable register that specifies the number of bytes to be read or
written in command access mode.
Initial value:
Initial value:
Bit
31 to 24
23 to 16
15 to 12
11 to 0
R/W:
R/W:
Bit:
Bit:
Data Counter Register (FLDTCNTR)
31
15
Bit Name
ECFLW[7:0] All 0
DTFLW[7:0] All 0
—
DTCNT[11:0] All 0
R
R
0
0
-
30
14
R
R
0
0
-
29
13
R
R
0
0
-
Initial
Value
All 0
ECFLW[7:0]
28
12
R
R
0
0
-
R/W
27
11
R
0
0
R/W Description
R
R
R
R/W Data Count Specification
R/W
26
10
R
0
0
FLECFIFO Access Count
Specify the number of longwords in FLECFIFO to be read
or written. These bit values are used when the CPU reads
from or writes to FLECFIFO.
In FLECFIFO read, these bits specify the number of
longwords of the data that can be read from FLECFIFO.
In FLECFIFO write, these bits specify the number of
longwords of unoccupied area that can be written in
FLECFIFO.
FLDTFIFO Access Count
Specify the number of longwords in FLDTFIFO to be read
or written. These bit values are used when the CPU reads
from or writes to FLDTFIFO.
In FLDTFIFO read, these bits specify the number of
longwords of the data that can be read from FLDTFIFO.
In FLDTFIFO write, these bits specify the number of
longwords of unoccupied area that can be written in
FLDTFIFO.
Reserved
These bits are always read as 0. The write value should
always be 0.
Specify the number of bytes of data to be read or written
in command access mode. (Up to 2048 + 64 bytes can be
specified.)
R/W
25
R
0
9
0
Section 22 AND/NAND Flash Memory Controller (FLCTL)
R/W
24
R
0
8
0
R/W
23
R
0
7
0
DTCNT[11:0]
Rev. 3.00 Sep. 28, 2009 Page 1069 of 1650
R/W
22
R
0
6
0
R/W
21
R
0
5
0
R/W
20
DTFLW[7:0]
R
0
4
0
R/W
19
R
0
3
0
REJ09B0313-0300
R/W
18
R
0
2
0
R/W
17
R
0
1
0
R/W
16
R
0
0
0