R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 89

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

(11) Absolute Address
When data is accessed by an absolute address, the absolute address value should be placed in the
memory table in advance. That value is transferred to the register by loading the immediate data
during the execution of the instruction, and the data is accessed in register indirect addressing
mode.
With the SH-2A, when data is referenced using an absolute address not exceeding 28 bits, it is also
possible to transfer immediate data located in the instruction code to a register and to reference the
data in register indirect addressing mode. However, when referencing data using an absolute
address of 21 to 28 bits, an OR instruction must be used after the data is transferred to a register.
Table 2.6
(12) 16-Bit/32-Bit Displacement
When data is accessed by 16-bit or 32-bit displacement, the displacement value should be placed
in the memory table in advance. That value is transferred to the register by loading the immediate
data during the execution of the instruction, and the data is accessed in the indexed indirect
register addressing mode.
Table 2.7
Classification
Up to 20 bits
21 to 28 bits
29 bits or more
Classification
16-bit displacement
Absolute Address Accessing
Displacement Accessing
SH-2A CPU
MOVI20
MOV.B
MOVI20S
OR
MOV.B
MOV.L
MOV.B
.DATA.L
SH-2A CPU
MOV.W
MOV.W
.DATA.W
#H'12345,R1
@R1,R0
#H'12345,R1
#H'67,R1
@R1,R0
@(disp,PC),R1
@R1,R0
H'12345678
..................
@(disp,PC),R0
@(R0,R1),R2
..................
H'1234
Rev. 3.00 Sep. 28, 2009 Page 57 of 1650
Example of Other CPU
MOV.W
Example of Other CPU
MOV.B
MOV.B
MOV.B
@(H'1234,R1),R2
@H'12345,R0
@H'1234567,R0
@H'12345678,R0
REJ09B0313-0300
Section 2 CPU