R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 413

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Table 9.21 Conditions for Determining Number of Idle Cycles
No. Condition
[1]
[2]
[3]
[4]
DMAIW[2:0] in
CMNCR
IW***[2:0] in
CSnBCR
SDRAM-related
bits in
CSnWCR
WM in
CSnWCR
Description
These bits specify the number of
idle cycles for DMA single address
transfer. This condition is effective
only for single address transfer and
generates idle cycles after the
access is completed.
These bits specify the number of
idle cycles for access other than
single address transfer. The
number of idle cycles can be
specified independently for each
combination of the previous and
next cycles. For example, in the
case where reading CS1 space
followed by reading other CS
space, the bits IWRRD[2:0] in
CS1BCR should be set to B'100 to
specify six or more idle cycles. This
condition is effective only for access
cycles other than single address
transfer and generates idle cycles
after the access is completed.
These bits specify precharge
completion and startup wait cycles
and idle cycles between commands
for SDRAM access. This condition
is effective only for SDRAM access
and generates idle cycles after the
access is completed
This bit enables or disables external
WAIT pin input for the memory
types other than SDRAM. When
this bit is cleared to 0 (external
WAIT enabled), one idle cycle is
inserted to check the external WAIT
pin input after the access is
completed. When this bit is set to 1
(disabled), no idle cycle is
generated.
Range Note
0 to 12 When 0 is specified for the
0 to 12 Do not set 0 for the number of
0 to 3
0 or 1
Rev. 3.00 Sep. 28, 2009 Page 381 of 1650
Section 9 Bus State Controller (BSC)
number of idle cycles, the
DACK signal may be asserted
continuously. This causes a
discrepancy between the
number of cycles detected by
the device with DACK and the
DMAC transfer count, resulting
in a malfunction.
idle cycles between memory
types which are not allowed to
be accessed successively.
accordance with the
specification of the target
SDRAM.
Specify these bits in
REJ09B0313-0300