R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1140

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 USB 2.0 Host/Function Module (USB)
Rev. 3.00 Sep. 28, 2009 Page 1108 of 1650
REJ09B0313-0300
Bit
8
7
6
Bit Name
WKUP
RWUPE
USBRST
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Wakeup Output
This bit is used to control remote wakeup signal
output to the USB bus. The module controls the
output time of a remote wakeup signal. When this bit
is set to 1, this module clears this bit to 0 after
outputting the 10-ms K state.
According to the USB specification, the USB bus idle
state must be kept for 5 ms or longer before a
remote wakeup signal is output. If this module writes
1 to this bit right after detection of suspended state,
the K state will be output after 2 ms.
0: Outputs no signals
1: Outputs a remote wakeup signal
Note: Do not write 1 to this bit, unless the device
Wakeup Detection Enable
Outputs a resume signal to a down port when a
remote wakeup signal is detected, by setting this bit
to 1. At this time, this module sets the RESUME bit
to 1.
0: Down-port wakeup is disabled.
1: Down-port wakeup is enabled.
Note: In setting this bit to 1, do not stop the USBCLK
Bus Reset Output
Outputs a USB bus reset signal by setting this bit to
1. The USB bus reset signal output time should be
controlled by software. This bit should be cleared to
0 after the USB bus reset time has elapsed.
0: USB bus reset signal output is stopped.
1: USB bus reset signal is output.
state is in the suspended state (the DVSQ bit in
the INTSTS0 register is set to 1xx) and the
USB host enables the remote wakeup signal.
When this bit is set to 1, the USBCLK must not
be stopped even in the suspended state.
even in the suspended state.