R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 13

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Section 6 Interrupt Controller (INTC) ...............................................................149
6.1
6.2
6.3
Resets ................................................................................................................................. 129
5.2.1
5.2.2
5.2.3
5.2.4
Address Errors ................................................................................................................... 133
5.3.1
5.3.2
Register Bank Errors.......................................................................................................... 135
5.4.1
5.4.2
Interrupts............................................................................................................................ 136
5.5.1
5.5.2
5.5.3
Exceptions Triggered by Instructions ................................................................................ 139
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
When Exception Sources Are Not Accepted ..................................................................... 143
Stack Status after Exception Handling Ends...................................................................... 144
Usage Notes ....................................................................................................................... 146
5.9.1
5.9.2
5.9.3
5.9.4
Features.............................................................................................................................. 149
Input/Output Pins ............................................................................................................... 151
Register Descriptions ......................................................................................................... 152
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
Input/Output Pins.................................................................................................. 129
Types of Reset ...................................................................................................... 129
Power-On Reset .................................................................................................... 130
Manual Reset ........................................................................................................ 132
Address Error Sources .......................................................................................... 133
Address Error Exception Handling ....................................................................... 134
Register Bank Error Sources................................................................................. 135
Register Bank Error Exception Handling ............................................................. 135
Interrupt Sources................................................................................................... 136
Interrupt Priority Level ......................................................................................... 137
Interrupt Exception Handling................................................................................ 138
Types of Exceptions Triggered by Instructions .................................................... 139
Trap Instructions ................................................................................................... 140
Slot Illegal Instructions ......................................................................................... 140
General Illegal Instructions................................................................................... 141
Integer Division Exceptions.................................................................................. 141
FPU Exceptions .................................................................................................... 142
Value of Stack Pointer (SP) .................................................................................. 146
Value of Vector Base Register (VBR) .................................................................. 146
Address Errors Caused by Stacking of Address Error Exception Handling ......... 146
Note before Exception Handling Begins Running................................................ 147
Interrupt Priority Registers 01, 02, 05 to 17 (IPR01, IPR02, IPR05 to IPR17) .... 153
Interrupt Control Register 0 (ICR0)...................................................................... 155
Interrupt Control Register 1 (ICR1)...................................................................... 156
Interrupt Control Register 2 (ICR2)...................................................................... 157
IRQ Interrupt Request Register (IRQRR)............................................................. 158
PINT Interrupt Enable Register (PINTER)........................................................... 160
Rev. 3.00 Sep. 28, 2009 Page xi of xxx
REJ09B0313-0300