R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 549

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

11.3.26 Timer Interrupt Skipping Counter (TITCNT)
TITCNT is an 8-bit readable/writable counter. The MTU2 has one TITCNT. TITCNT retains its
value even after stopping the count operation of TCNT_3 and TCNT_4.
Note: To clear the TITCNT, clear the bits T3AEN and T4VEN in TITCR to 0.
Bit
7
6 to 4
3
2 to 0
Bit Name
—
3ACNT[2:0]
—
4VCNT[2:0]
Initial value:
Initial
Value
0
000
0
000
R/W:
Bit:
R
7
0
-
R/W
R
R
R
R
R
6
0
3ACNT[2:0]
Description
Reserved
This bit is always read as 0.
TGIA_3 Interrupt Counter
While the T3AEN bit in TITCR is set to 1, the count in
these bits is incremented every time a TGIA_3 interrupt
occurs.
[Clearing conditions]
•
•
•
Reserved
This bit is always read as 0.
TCIV_4 Interrupt Counter
While the T4VEN bit in TITCR is set to 1, the count in
these bits is incremented every time a TCIV_4 interrupt
occurs.
[Clearing conditions]
•
•
•
R
5
0
When the 3ACNT2 to 3ACNT0 value in TITCNT
matches the 3ACOR2 to 3ACOR0 value in TITCR
When the T3AEN bit in TITCR is cleared to 0
When the 3ACOR2 to 3ACOR0 bits in TITCR are
cleared to 0
When the 4VCNT2 to 4VCNT0 value in TITCNT
matches the 4VCOR2 to 4VCOR2 value in TITCR
When the T4VEN bit in TITCR is cleared to 0
When the 4VCOR2 to 4VCOR2 bits in TITCR are
cleared to 0
R
4
0
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
R
3
0
-
Rev. 3.00 Sep. 28, 2009 Page 517 of 1650
R
2
0
4VCNT[2:0]
R
1
0
R
0
0
REJ09B0313-0300