R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 252

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Cache
(1)
The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data
is not valid.
The U bit (only for operand cache) indicates whether the entry has been written to in write-back
mode. When the U bit is 1, the entry has been written to; when 0, it has not.
The tag address holds the physical address used in the external memory access. It consists of 21
bits (address bits 31 to 11) used for comparison during cache searches. In this LSI, the addresses
of the cache-enabled space are H'00000000 to H'1FFFFFFF (see section 9, Bus State Controller
(BSC)), and therefore the upper three bits of the tag address are cleared to 0.
The V and U bits are initialized to 0 by a power-on reset but not initialized by a manual reset or in
software standby mode. The tag address is not initialized by a power-on reset or manual reset or in
software standby mode.
(2)
Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes).
The data array is not initialized by a power-on reset or manual reset or in software standby mode.
Rev. 3.00 Sep. 28, 2009 Page 220 of 1650
REJ09B0313-0300
Address Array
Data Array
Entry 127
Entry 0
Entry 1
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V U
23 (1 + 1 + 21) bits
Address array (ways 0 to 3)
Tag address
Figure 8.1 Operand Cache Structure
127
0
1
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LW0
LW0 to LW3: Longword data 0 to 3
LW1
128 (32 × 4) bits
Data array (ways 0 to 3)
LW2
LW3
127
0
1
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LRU
6 bits