R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 328

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 9 Bus State Controller (BSC)
9.4.7
RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1
and RTCNT is cleared to 0.
When the RFSH bit in SDCR is 1, a memory refresh request is issued by this matching signal.
This request is maintained until the refresh operation is performed. If the request is not processed
when the next matching occurs, the previous request is ignored.
The REFOUT signal can be asserted when a refresh request is generated while the bus is released.
For details, see the description of Relationship between Refresh Requests and Bus Cycles in
section 9.5.6 (9), Relationship between Refresh Requests and Bus Cycles, and section 9.5.13, Bus
Arbitration.
When the CMIE bit in RTCSR is set to 1, an interrupt request is issued by this matching signal.
The request continues to be output until the CMF bit in RTCSR is cleared. Clearing the CMF bit
only affects the interrupt request and does not clear the refresh request. Therefore, a combination
of refresh request and interval timer interrupt can be specified so that the number of refresh
requests are counted by using timer interrupts while refresh is performed periodically.
When RTCOR is written, the upper 16 bits of the write data must be H'A55A to cancel write
protection.
Initial value:
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 296 of 1650
REJ09B0313-0300
Bit
31 to 8
7 to 0
R/W:
R/W:
Bit:
Bit:
Refresh Time Constant Register (RTCOR)
Bit Name
⎯
31
15
R
R
0
0
-
-
30
14
R
R
0
0
-
-
29
13
R
R
0
0
-
-
Initial
Value
All 0
All 0
28
12
R
R
0
0
-
-
27
11
R
R
0
0
-
-
R/W Description
R
R/W 8-Bit Counter
26
10
R
R
0
0
-
-
Reserved
These bits are always read as 0.
25
R
R
0
9
0
-
-
24
R
R
0
8
0
-
-
R/W
23
R
0
7
0
-
R/W
22
R
0
6
0
-
R/W
21
R
0
5
0
-
R/W
20
R
0
4
0
-
R/W
19
R
0
3
0
-
R/W
18
R
0
2
0
-
R/W
17
R
0
1
0
-
R/W
16
R
0
0
0
-