R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 591

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

(2)
In complementary PWM mode, 6-phase PWM output is possible. Figure 11.39 illustrates counter
operation in complementary PWM mode, and figure 11.40 shows an example of complementary
PWM mode operation.
(a)
In complementary PWM mode, three counters—TCNT_3, TCNT_4, and TCNTS—perform
up/down-count operations.
TCNT_3 is automatically initialized to the value set in TDDR when complementary PWM mode
is selected and the CST bit in TSTR is 0.
When the CST bit is set to 1, TCNT_3 counts up to the value set in TGRA_3, then switches to
down-counting when it matches TGRA_3. When the TCNT3 value matches TDDR, the counter
switches to up-counting, and the operation is repeated in this way.
TCNT_4 is initialized to H'0000.
When the CST bit is set to 1, TCNT4 counts up in synchronization with TCNT_3, and switches to
down-counting when it matches TCDR. On reaching H'0000, TCNT4 switches to up-counting,
and the operation is repeated in this way.
TCNTS is a read-only counter. It need not be initialized.
When TCNT_3 matches TCDR during TCNT_3 and TCNT_4 up/down-counting, down-counting
is started, and when TCNTS matches TCDR, the operation switches to up-counting. When
TCNTS matches TGRA_3, it is cleared to H'0000.
When TCNT_4 matches TDDR during TCNT_3 and TCNT_4 down-counting, up-counting is
started, and when TCNTS matches TDDR, the operation switches to down-counting. When
TCNTS reaches H'0000, it is set with the value in TGRA_3.
TCNTS is compared with the compare register and temporary register in which the PWM duty is
set during the count operation only.
Outline of Complementary PWM Mode Operation
Counter Operation
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 3.00 Sep. 28, 2009 Page 559 of 1650
REJ09B0313-0300