mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1008

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

LCD Controller
18.3.9.3 ACTIVE INTERFACE. Active (TFT) interfaces use the following signals. These
signals have a programmable polarity. T
T
Figure 18-12, the reference to 1-16 lines signifies that the time period depends on how the
the VPW field in the LCVCR register. The reference to 0-1,023 lines signifies that the time
period varies between 0 and 1,023 scan lines (WBF field in the LCVCR).
Use the following formulas to calculate the HSYNC and VSYNC cycles using the
user-programmable parameters that are located in the LCD control registers.
Where:
delay
• SHIFT/CLK—When the LCD output enable signal is valid, data is latched on the
• FRAME/VSYNC—This vertical sync signal initiates a new frame.
• LOAD/HSYNC—This horizontal sync signal initiates a new line.
• LCD_AC/LOE—When the LCD output enable signal is valid, it enables data to be
• LD—The LCD data bus represents 4-, 8-, or 12-bit data. For monochrome displays,
asserted edge of CLK.
shifted into the display. When it is disabled, the data is invalid and no data is transferred.
4- or 8-bit data is the same as passive interfaces and 12-bit data is used for color
displays.
VSYNC = (HSYNC
HSYNC = SHIFT/CLK
SHIFT/CLK = LCDCLK K
LCDCLK = VCOOUT LCD_div_factor (programmed)
L = Number of lines in panel ( 2 for dual-scan displays and +VPW in LCVCR for active).
WBF = Number of waits between frames.
P = Number of pixels per line in panel ( 2 for dual-scan displays).
LCDBW = LCD bus width (4- or 8-bit for passive displays and 1 for active).
TWBL = WBL + N = Total number of waits between lines.
VCOOUT = SPLL output frequency.
LCD_div_factor = LCD_div_factor is programmed in the SCCR (DFLCD
K = Inner rate factor that depends on your configuration:
is a circuit delay that is specified in Section 22 DC Electrical Characteristics . In
3:
2:
1:
For a 4-bit per pixel color passive display with an 8-bit LCD data bus width
single-scan.
For a 4-bit per pixel color passive display with an 8-bit LCD data bus width
dual-scan or with a 4-bit LCD data bus width single-scan.
For all other configurations.
Freescale Semiconductor, Inc.
For More Information On This Product,
L) +WBF
(P
MPC823 REFERENCE MANUAL
LCDBW +12 + TWBL)
Go to: www.freescale.com
cyc
is the cycle time of the LCD clock (SHIFT/CLK).
DFALCD).
MOTOROLA