mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 567

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
Communication Processor Module
Time-slot assigner programming is completely independent of the protocol used by the
serial communication controller or serial management controller. For instance, the fact that
serial communication controller can be programmed for the HDLC protocol has no impact
on time-slot assigner programming. The purpose of the time-slot assigner is to route the
data from the specified pins to the serial communication controller or serial management
controller at the correct time, but it is the responsibility of the SCC or SMC to handle the
received data. In its simplest mode, the time-slot assigner identifies the frame using one
sync pulse and one clock signal that you provide. This can be enhanced to allow
independent routing of the receive and transmit data on the TDMA channel. Additionally, the
definition of a time-slot need not be limited to 8 bits or even to a single contiguous position
within the frame. You can provide separate receive and transmit syncs as well as clocks.
These various configurations are illustrated in Figure 16-44.
The time-slot assigner can support two, independent, half-duplex TDM sources, one in
reception and one in transmission, using two sync inputs and two input clocks. In addition
to channel programming, the time-slot assigner supports up to eight strobe outputs that may
be asserted on a bit or byte basis. These strobes are completely independent from the
channel routing used by SCCs and the SMCs. They are useful for interfacing to other
devices that do not support the multiplexed interface or for enabling/disabling three-state I/
O buffers in a multi-transmitter architecture.
Most time-slot assigner programming is accomplished in two 64
16-bit serial interface
RAMs that are directly accessible by the host CPU in the internal register section of the
MPC823 and are not associated with the dual-port RAM. One serial interface RAM is always
used to program the transmit routing and the other is used to program the receive routing.
With the serial interface RAMs, you can define the number of bits or bytes to be routed to
the serial communication controller or serial management controller and decide when the
external strobes are to be asserted and negated.
The size of the serial interface RAM that is available for time-slot programming depends on
the configuration of the RDM field in the SIGMR. If on-the-fly changes are allowed, the serial
interface RAM entries are reduced by one-half. However, the serial interface RAM size is
sufficient to allow extensive time-slot programming flexibility. The maximum frame length
that can be supported in any configuration is 8,192 bits. The serial interface supports two
testing modes—echo and loopback. The echo mode provides a return signal from the
physical interface by retransmitting the signal it has received.
The physical interface echo mode differs from the individual SCC echo mode in that it can
operate on the entire TDM signal, rather than just on a particular SCC channel. The
loopback mode causes the physical interface to receive the same signal it is transmitting.
The serial interface loopback mode conducts a more thorough check than the individual
SCC loopback does. It also checks the serial interface and the internal channel routes. The
maximum external serial clock that may be an input to the time-slot assigner is GCLK2 2.5.
If a serial communication controller or serial management controller is operating with the
NMSI, then the serial clock rate may be slightly faster at a value not to exceed GCLK2
2.
MPC823 REFERENCE MANUAL
16-115
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