mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1326

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

I2CSCL,
I2CSDA,
I2MOD,
I-address,
IC_ADR,
IC_CST,
IC_DAT,
icbi,
ICR,
ICTRL,
IDG (definition),
IDL (definition),
IDL interface
idle condition (definition),
IDMA
IDMA transfers, performing,
IDMA,
IDMA1 and 2 mask register,
IDMA1 and 2 status register,
IDMRx,
IDSRx,
IFG (definition),
IIR
IIR,
image sizes, switching between,
IMMR,
implementation
implementing a precise exception model,
IN token,
infra-red encoder/decoder,
initialization
implementation,
operation,
programming
programming,
buffer descriptors,
commands,
edge-sensitive mode,
features,
interface signals,
level-sensitive mode,
operand transfers,
operation,
parameter RAM memory map,
single address mode,
single-buffer burst fly-by mode,
starting,
transfers,
applications,
coefficients and sample data buffers,
function descriptor,
parameter packet,
IDL interface,
SCCx ASYNC HDLC,
16-57
11-48
20-55
16-89
3-1
6-17
16-94
example,
16-95
16-465
2-9
9-5
9-7
2-9
9-6
16-354
20-9
,
6-18
,
16-101
16-90
20-45
16-101
,
,
16-141
16-90
16-109
16-110
16-141
16-263
16-263
16-100
,
16-59
16-146
12-34
16-142
16-145
16-142
16-90
16-96
16-59
16-102
16-58
16-198
16-101
16-101
16-103
16-270
16-195
16-91
Freescale Semiconductor, Inc.
16-95
16-94
For More Information On This Product,
19-4
16-92
,
,
16-105
16-110
16-109
MPC823 REFERENCE MANUAL
16-57
6-8
Go to: www.freescale.com
instruction address,
instruction cache
instruction cache address register,
instruction cache control and status register,
instruction cache data port register,
instruction cache,
instruction cache, how to disable,
instruction cache, how to enable,
instruction cache, how to inhibit,
instruction execution timing examples,
instruction execution timing,
instruction fetch show cycles,
instruction flow (illustration),
instruction register,
instruction, long latency,
instructions
of the control registers,
SCCx in UART mode example,
serial communication controllers,
universal serial bus example,
coherency,
commands
commands,
data path block diagram,
debug support,
features,
instruction fetch on a predicted path,
invalidating,
operation,
reading,
reset,
restoring the state of,
restrictions,
special purpose control registers,
updating code and memory region attributes,
writing,
add,
addc,
adde,
addi,
addic,
addic.,
addis,
addme,
addze,
B-1
9-14
CACHE DISABLE,
CACHE ENABLE,
INSTRUCTION CACHE BLOCK
INVALIDATE ALL,
LOAD & LOCK,
UNLOCK ALL,
UNLOCK LINE,
B-7
B-10
INVALIDATE,
B-8
9-14
B-9
B-11
B-13
B-12
9-14
9-12
9-1
9-7
9-14
9-14
9-8
9-9
9-1
9-14
21-19
20-9
9-11
9-10
9-10
9-9
6-9
9-15
9-11
9-9
9-11
6-24
8-1
6-3
9-4
20-8
9-11
9-11
16-375
9-11
9-6
16-227
9-7
16-185
9-4
8-4
9-8
,
Index-13
16-377
Index
9-5