mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1040
mpc823rg
Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MPC823RG.pdf
(1348 pages)
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Video Controller
19.3.7 Video Frame Buffer B Start Address Register (Set 0)
The 32-bit video frame buffer B start address register set 0 (VFBA0) holds the start address
of the set_0 even field. Since all bursts must be 16-byte aligned, this register does not use
the four least-significant bits of the address.
FBA0—Frame Buffer B Start Address for Set 0
This field designates the start address of the frame buffer B set 0 in system memory.
VFBA0
NOTE: X = “Don’t Care” and — = Undefined.
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
16
0
17
1
18
2
Freescale Semiconductor, Inc.
For More Information On This Product,
19
3
20
MPC823 REFERENCE MANUAL
4
Go to: www.freescale.com
21
5
FBA0
R/W
(IMMR & 0xFFFF0000) + 0x81A
(IMMR & 0xFFFF0000) + 0x818
—
22
6
23
7
FBA0
R/W
—
24
8
25
9
10
26
11
27
12
28
13
29
R/W
—
X
MOTOROLA
14
30
15
31
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