mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 665

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

• Framing Error — The SCCx UART controller gets this error when it receives a character
• Break Sequence Error — The SCCx UART controller provides flexible break support to
with no stop bit. All framing errors are reported by the SCCx UART controller,
regardless of its mode. When this error occurs, the channel writes the received
character to the buffer, closes it, sets the FR bit in the RX buffer descriptor, and
generates the RX interrupt if it is enabled. The channel also increments FRMEC. When
this error occurs, parity is not checked for this character. In automatic multidrop mode,
the receiver immediately enters hunt mode. If the RZS and SYN bits are set in the
PSMR–SCC UART register when the SCCx UART controller is in synchronous mode,
the receiver reports all framing errors, but continues reception if the unexpected zero is
really the start bit of the next character. If RZS is set, your software may not consider a
reported SCCx UART framing error as a true framing error, unless two or more framing
errors occur within a short period of time.
the receiver. When the first break sequence is received, the SCCx UART controller
increments the BRKEC and issues the break start event in the SCCE–UART register,
which can generate an interrupt if it is enabled. The SCCx UART controller then
measures the break length and, when the break sequence is complete, writes the
length to the BRKLN register. After the first one is received, the SCCx UART controller
also issues the break end event in the SCCE–UART register, which can generate an
interrupt if it is enabled. If the SCCx UART controller was in the process of receiving
characters when the break was received, it also closes the receive buffer, sets the BR
bit in the RX buffer descriptor, and writes the RX bit in the SCCE–UART register, which
can generate an interrupt if it is enabled. If the RZS bit is set in the PSMR–SCC UART
register when the SCCx UART controller is in synchronous mode, then a break
sequence is detected after only two successive break characters are received.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
Communication Processor Module
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