mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 226

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

11.5.1 Level One Descriptor
The following table describes the hardware-assisted level one descriptor format that
minimizes the software tablewalk routine.
L2BA—Level 2 Table Base Address
This field contains a pointer to a base address of the level 2 table. Bits 18 and 19 are only
used when MD_CTR
Bits 20–22—Reserved
These bits are reserved and must be set to 0.
APG—Access Protection Group
This field contains access protection for the entire memory segment associated with this
entry of the table.
G—Guarded Storage Attribute for Entry
PS—Page Size Level One
WT—Writethrough Attribute for Entry
LEVEL ONE DESCRIPTOR FORMAT
NOTE: — = Undefined. The default values depend on the state of system memory.
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
0 = Unguarded storage.
1 = Guarded storage.
00 = Small (4K or 16K).
01 = 512K.
11 = 8M.
10 = Reserved.
0 = Copyback cache policy region (default).
1 = Writethrough cache policy region.
16
0
17
1
L2BA
R/W
—
18
TWAM
2
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For More Information On This Product,
19
= 1. Otherwise, they must be set to 0.
3
20
MPC823 REFERENCE MANUAL
4
RESERVED
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R/W
21
—
5
SYSTEM MEMORY XXXXX0000
SYSTEM MEMORY XXXXX002
22
6
23
7
L2BA
R/W
—
24
8
APG
R/W
—
25
9
10
26
R/W
11
27
—
G
Memory Management Unit
12
28
R/W
PS
—
13
29
R/W
WT
14
30
—
R/W
11-9
15
31
—
V