mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 799

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

16.10 UNIVERSAL SERIAL BUS CONTROLLER
The universal serial bus (USB) is an industry standard extension to the PC architecture. The
USB controller allows the MPC823 to exchange data with a PC host. It supports data
exchanges between a host computer and a wide range of simultaneously accessible
peripherals. The attached peripherals share USB bandwidth through a host scheduled
token-based protocol. The USB physical interconnect is a tiered star topology. A hub is at
the center of each star. Each wire segment is a point-to-point connection between the host
and a hub or function or a hub connected to another hub/function. There is only one host in
any USB system. The USB transfers signals and power over a four-wire cable. The
signalling occurs over two wires and point-to-point segments. The USB full-speed signalling
bit rate is 12Mbps. A limited capability low-speed signalling mode is also defined at 1.5Mbps.
The MPC823 USB controller consists of a transmitter module, receiver module, and two
protocol state machines. The protocol state machines control the receiver and transmitter
modules. One state machine implements the function state diagram and the other
implements the host state diagram. The MPC823 USB controller is capable of implementing
a USB function endpoint, a USB host, or both for testing purposes (loop-back diagnostics).
Figure 16-109 illustrates the USB controller block diagram.
For USB implementation, it is recommended that you get a copy of the USB Specification
as a supplement to this manual. You can download a copy from http://www.usb.org.
31. Write 0x1088000C to the GSMR_L to configure the CTS2 (CLSN) and CD2 (RENA)
32. Write 0xD555 to the DSR.
33. Set the PSMR–SCC Ethernet to 0x0A0A to configure 32-bit CRC, promiscuous mode
34. Enable the TENA pin (RTS2). Since the MODE field of the GSMR_L is written to
35. Write 0x1088003C to the GSMR_L register to enable the SCC2 transmitter and
pins to automatically control transmission and reception (DIAG field) and the Ethernet
mode. TCI is set to allow more setup time for the EEST to receive the MPC82 transmit
data. TPL and TPP are set for Ethernet requirements. The DPLL is not used with
Ethernet. Notice that the transmitter (ENT) and receiver (ENR) have not been enabled
yet.
and begin searching for the start frame delimiter 22 bits after RENA.
Ethernet, the TENA signal is low. Write PCPAR bit 14 with a one and PCDIR bit 14
with a zero.
receiver. This additional write ensures that the ENT and ENR bits are enabled last.
Note: After 14 bytes and the 46 bytes of automatic pad (plus the 4 bytes of CRC) are
transmitted, the TX buffer descriptor is closed. Additionally, the receive buffer is
closed after a frame is received. Any data received after 1,520 bytes or a single
frame causes a busy (out-of-buffers) condition since only one RX buffer
descriptor is prepared.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
Communication Processor Module
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