mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 344

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

External Bus Interface
13.4.10 Storage Reservation Protocol
The MPC823 storage reservation protocol supports multilevel bus structure. For each local
bus, storage reservation is handled by the local reservation logic. The protocol tries to
optimize reservation cancellation so that a PowerPC processor is notified of storage
reservation loss on a remote bus only when it has issued a stwcx cycle to that address. In
other words, the reservation loss indication comes as part of the stwcx cycle. This method
avoids the need to have fast storage reservation loss indication signals routed from every
remote bus to every PowerPC master.
The storage reservation protocol makes the following assumptions:
• Each processor has, at most, one reservation “flag”
• lwarx sets the reservation “flag”
• lwarx by the same processor clears the reservation “flag” related to a previous lwarx
• stwcx by the same processor clears the reservation “flag”
• A store by the same processor does not clear the reservation “flag”
• Some other processor (or other mechanism) store to the same address as an existing
• If the storage reservation is lost it is guaranteed that stwcx will not modify the storage
instruction and again sets the reservation “flag”
reservation clears the reservation “flag”
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
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