mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 750

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
16.9.21 The SCCx in Transparent Mode
The SCCx in Transparent mode allows serial data to be transmitted and received over a
serial communication controller without any modification to the datastream. Transparent
mode provides a clear channel on which a serial communication controller does not perform
bit-level manipulation. Any protocol that uses the transparent mode must have a software
layer that loads the parameters. SCCx in Transparent mode functions as a high-speed
serial-to-parallel and parallel-to-serial converter. This mode is also referred to as a totally
transparent or promiscuous operation.
There are several basic applications for transparent mode. First, some data needs to be
moved serially, but requires no superimposed protocol. Second, some board-level
applications require a serial-to-parallel and parallel-to-serial conversion that allows
communication between chips on the same board. Third, some applications require the data
to be switched without interfering with the protocol encoding itself. For instance, in a
multiplexer, data from a high-speed time-multiplexed serial stream is multiplexed into
multiple low-speed datastreams. The objective is to switch the data path without altering the
protocol encoded on that data path.
By appropriately setting the GSMR_L, the SCCx channels can be configured to function in
Transparent mode. The MPC823 receives and transmits the entire serial bitstream
transparently. This mode is configured by selecting the TTX and TRX bits in the GSMR_H
for the transmitter and receiver, respectively. However, both bits must be set for full-duplex
transparent operation.
17. Write 0x00009980 to the GSMR_H to configure the transparent channel. The CDS
18. Write 0x00000000 to the GSMR_L. Normal operation of the transmit clock is used (TCI
19. Write 0x031c to the IRSIP register. When working with Timer 2 as the SIP trigger, the
20. Write 0x0005 to the IRMODE register to enable the infrared and to set the mode of
21. Program TMR2 register when working with Timer 2 as the SIP trigger.
22. Write 0x00000030 to the GSMR_L to enable the SCC2 transmitter and receiver. This
and CTSS bits must be set to one. The TDCR, RDCR, RENC, and TENC fields must
be set to zero.
bit is cleared). Notice that the transmitter (ENT) and receiver (ENR) have not been
enabled yet.
value must be 0x231c.
operation to high-speed.
additional write ensures that the ENT and ENR bits will be enabled last.
Note: After 5 bytes have been transmitted, the TX buffer descriptor is automatically
closed. Once a complete frame is received, the RX buffer descriptor is closed.
Any data received after 16 bytes or a single frame causes a busy (out-of-buffers)
condition since only one RX buffer descriptor is prepared.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
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