mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 684

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
Communication Processor Module
To rearrange the transmit queue before the communication processor module finishes
transmitting all of the buffers, issue the STOP TRANSMIT command. This can be useful for
transmitting expedited data before previously linked buffers or when an error occurs. When
receiving the STOP TRANSMIT command, the SCCx HDLC controller stops transmitting
the current frame and starts transmitting idles or flags. When the SCCx HDLC controller
receives the RESTART TRANSMIT command, it resumes transmission. To insert a
high-priority frame without aborting the current frame, the GRACEFUL STOP TRANSMIT
command can be issued. A special interrupt can be generated in the event register when
the current frame is complete.
16.9.16.3 SCCx HDLC CHANNEL FRAME RECEPTION PROCESS.The HDLC receiver
is designed to operate with little or no intervention from the core and can perform address
recognition, CRC checking, and maximum frame length checking. You are free to use the
received frame to perform any HDLC-based protocol.
When the core enables one of the receivers, the receiver waits for an opening flag character
and when it detects the first byte of the frame, the SCCx HDLC controller compares the
frame address against the user-programmable addresses. You have four 16-bit address
registers and an address mask available for address matching. The SCCx HDLC controller
compares the received address field to the user-defined values after masking with the
address mask. The SCCx HDLC controller can also detect broadcast (all ones) address
frames if one address register is written with all ones.
If a match is detected, the SCCx HDLC controller fetches the next buffer descriptor and if it
is empty, it starts transferring the incoming frame to the buffer descriptor associated data
buffer. When the data buffer has been filled, the SCCx HDLC controller clears the E bit in
the buffer descriptor and generates an interrupt if the I bit in the buffer descriptor is set. If
the incoming frame exceeds the length of the data buffer, the SCCx HDLC controller fetches
the next buffer descriptor in the table and, if it is empty, continues transferring the rest of the
frame to this buffer descriptor associated data buffer.
During this process, the SCCx HDLC controller checks for a frame that is too long. When
the frame ends, the CRC field is checked against the recalculated value and written to the
data buffer. The data length written to the last buffer descriptor in the HDLC frame is the
length of the entire frame. This enables HDLC protocols that “lose” frames to correctly
recognize the frame-too-long condition. The SCCx HDLC controller then sets the last buffer
in the frame bit, writes the frame status bits into the buffer descriptor, and clears the E bit.
The SCCx HDLC controller next generates a maskable interrupt, indicating that a frame has
been received and is in memory. The SCCx HDLC controller then waits for a new frame.
Back-to-back frames can be received with only a single shared flag between frames.
In the received frames threshold (RFTHR) location of the parameter RAM, you can configure
the SCCx HDLC controller not to interrupt the core until a certain number of frames are
received. You can combine this function with a timer to implement a timeout if less than the
threshold number of frames are received.
MPC823 REFERENCE MANUAL
MOTOROLA
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