mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1150

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
APPENDIX A
SERIAL COMMUNICATION PERFORMANCE
Operating at 25MHz, the MPC823 is designed to support unrestricted operation of the
high-level data link control (HDLC) or transparent protocol running on the serial
communication controllers at 2.048Mbps. The MPC823 can also support one Ethernet
channel at 10Mbps and one HDLC or transparent channel at 1Mbps. The physical clocking
limit of the serial communication controllers is higher than the sustained serial bit rate. This
limit is given as a 1:2.25 ratio between the sync clock, which is a clock generated in the clock
synthesizer that can be as fast as the 25MHz system clock and the serial clock. For
example, with a sync clock of 25MHz, the serial communication controllers can be clocked
at 11.1MHz. This clocking scheme allows the serial communication controllers to handle
high-speed bursts of data bits for short periods of time subject to the FIFO sizes.
When the serial communication controllers are connected to a time-division multiplexed
channel using the time-slot assigner on the MPC823, a serial communication controller’s
physical clocking limit is a 1:2.5 ratio between the sync clock and serial clock. Therefore, the
serial communication controllers can be connected to a 10.0MHz time-division multiplexed
channel with a 25MHz MPC823. This clocking scheme allows it to handle high-speed bursts
of data bits for short periods of time subject to the FIFO sizes. Other devices that offer a
higher HDLC performance than the MPC823 are the Motorola MC68605 1984 CCITT X.25
LAPB controller and MC68606 CCITT Q.921 multilink LAPD controller. The MC68605 and
MC68606 perform the full data-link layer protocol and support various transparent modes
within HDLC-framed operation at a minimum 10Mbps. The performance figures listed in
Table A-1 are for a 25MHz system clock. Notice that, in general, performance scales linearly
with the frequency, so that a combination of protocols over the MPC823’s performance
limitation at 25MHz can occur at 50MHz.
MPC823 REFERENCE MANUAL
A-1
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