mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 797

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

16.9.23.5 SCCx ETHERNET MASK REGISTER. When a serial communication controller
is in Ethernet mode, the 16-bit read/write SCCx mask register is referred to as the SCCx
Ethernet mask register (SCCM–Ethernet). Since each protocol has specific requirements,
the SCCM bits are different for each implementation. This register has the same bit formats
as the SCCE–Ethernet register. If a bit in the SCCM–Ethernet register is a 1, the
corresponding interrupt in the SCCE–Ethernet register is enabled. If the bit is zero, the
corresponding interrupt in the SCCE–Ethernet register is masked.
16.9.23.6 SCCx ETHERNET STATUS REGISTER. Since all Ethernet mode selections are
in the GSMR_x and PSMR registers, the SCCx Ethernet status register (SCCS–Ethernet)
is not used when an SCCx is in Ethernet mode. The current state of the RENA and CLSN
signals can be found in port C, which is described in Section 16.14.9 Port C Registers.
16.9.23.7 SCC2 ETHERNET PROGRAMMING EXAMPLE. The following is an example
initialization sequence for the SCC2 in Ethernet mode. The CLK1 pin is used for the Ethernet
receiver and the CLK2 pin is used for the transmitter.
SCCM–ETHERNET
RESET
FIELD
ADDR
1. Configure the port A pins to enable the TXD1 and RXD1 pins. Write PAPAR bits 12
2. Configure the port C pins to enable CTS2 (CLSN) and CD2 (RENA). Write PCPAR and
3. Do not enable the RTS2 (TENA) pin yet because the pin is still functioning as RTS and
4. Configure port A to enable the CLK1 and CLK2 pins. Write PAPAR bits 7 and 6 with
5. Connect the CLK1 and CLK2 pins to SCC2 using the serial interface. Write the R2CS
6. Connect the SCC2 to the NMSI and clear the SC2 bit in the SICR.
7. Initialize the SDMA configuration register (SDCR) to 0x0001.
8. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RX buffer
R/W
BIT
and 13 with ones, PADIR bits 12 and 13 with zeros, and PAODR bit 13 with zero.
PCDIR bits 9 and 8 with zeros and PCSO bits 9 and 8 with ones.
transmission on the LAN could accidentally begin.
ones and PADIR bits 7 and 6 with zeros.
field in the SICR to 101 and the T2CS field to 100.
descriptor and TX buffer descriptor in the dual-port RAM. Assuming one RX buffer
descriptor at the beginning of the dual-port RAM and one TX buffer descriptor following
that RX buffer descriptor, write RBASE with 0x2000 and TBASE with 0x2008.
0
1
2
Freescale Semiconductor, Inc.
RESERVED
For More Information On This Product,
3
R/W
0
MPC823 REFERENCE MANUAL
4
Go to: www.freescale.com
5
(IMMR & 0xFFFF0000) + 0xA34
6
7
GRA RESERVED TXE
R/W
8
0
9
R/W
Communication Processor Module
0
10
R/W
11
0
RXF
R/W
12
0
BSY
R/W
13
0
TXB
R/W
14
0
16-345
RXB
R/W
15
0