mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 260

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

UWP3—Problem (User) Write Permission Page Three
11.6.3 MMU Instruction Content-Addressable Registers
The MI_CAM, MI_RAM0, and MI_RAM1 registers are interface registers that allow you to
read the data memory management unit CAM and RAM entries. If you try to write to the
MI_CAM register using the mtspr instruction, the CAM and RAM values of the entry indexed
by the DTLB_INDX field to MI_CAM, MI_RAM0, and MI_RAM1 will be loaded. The source
register in the mtspr instruction can be any register, since its value is not used. The values
of the MI_CAM, MI_RAM0, and MI_RAM1 registers can be read using the mfspr instruction.
If you try to write to the MI_RAM0 and MI_RAM1 registers using the mtspr instruction, it will
be considered a NOP (no operation) instruction.
11.6.3.1 MMU INSTRUCTION CAM ENTRY READ REGISTER. When the
content-addressable memory of the MMU instruction CAM entry read (MI_CAM) register is
read, it contains the effective address and page sizes of an entry indexed by the ITLB_INDX
field of the MI_CTR. This register is only updated when you write a value to it.
EPN—Effective Page Number
These bits are the most-significant bits of the page’s effective address.
MI_CAM
NOTE: — = Undefined.
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
0 = Subpage 3 (address[20:21]=11) problem write access is not permitted.
1 = Subpage 3 (address[20:21]=11) problem write access is permitted.
16
0
17
1
EPN
—
R
18
2
Freescale Semiconductor, Inc.
For More Information On This Product,
19
3
20
MPC823 REFERENCE MANUAL
4
Go to: www.freescale.com
PS
21
—
R
5
22
6
23
SPR 816
SPR 816
7
EPN
—
R
24
8
ASID
—
R
25
9
10
26
SH
11
27
—
R
Memory Management Unit
12
28
13
29
SPV
—
R
14
30
11-43
15
31