mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1018

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
LCD Controller
18.4.4 LCD Frame Buffer A Start Address Register
The 32-bit LCD frame buffer A start address (LCFAA) register contains the start address of
the frame buffer data that you want to send to your LCD panel. FIFO A is the destination for
your frame buffer data. For single-scan panels, FIFO A concatenated with FIFO B is used
to transfer data, so only the LCFAA register needs to be loaded. The DMA controller uses
the buffer start address to initiate data transfers from display memory, which can be system
memory or a dedicated display memory block. Because all LCD controller DMA bursts must
be 16-byte aligned, the four least-significant bits of the address are not used. This register
is read by the LCD controller at the start of each frame. Therefore, changing this register will
not take effect until the WBF bit expires.
FAA—FIFO A Address
This field designates the start address in display or system memory where LCD panel data
resides.
LCFAA
NOTE: X - “Don’t Care” and — = Undefined.
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
16
0
17
1
18
2
Freescale Semiconductor, Inc.
For More Information On This Product,
19
3
20
MPC823 REFERENCE MANUAL
4
Go to: www.freescale.com
21
5
FAA
R/W
(IMMR & 0xFFFF0000) + 0x852
IMMR & 0xFFFF0000 + 0x850
22
6
23
7
FAA
R/W
24
8
25
9
10
26
11
27
12
28
13
29
R/W
X
MOTOROLA
14
30
15
31

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