mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 132

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

The PowerPC Core
6.2 BASIC STRUCTURE OF THE CORE
To accomplish its tasks, the core is divided into the following subunits:
6.2.1 Instruction Flow Within the Core
When fetched, instructions enter the instruction queue and enable branch folding by
allowing out-of-order branch execution. Nonbranch instructions reaching the top of the
instruction queue are issued to the execution units. Instructions can be flushed from the
instruction queue in case of an exception on a previous instruction, interrupt, or
miss-predicted fetch.
All instructions, including branches, enter the history buffer along with processor state
information that can be affected by the instruction’s execution. This information is used to
enable out-of-order completion of instructions together with precise exception handling.
When exceptions or interrupts occur, instructions can be flushed or recovered from the
machine. The instruction queue is always flushed when the history buffer is recovered. An
instruction retires from the machine after it finishes executing without exception and all
preceding instructions are retired from the machine. Figure 6-1 illustrates the core’s
microarchitecture.
• Sequencer Unit —Consists of the branch processor (next address generation), the
• Register Unit —Consists of all the user-visible registers, the register’s scoreboard
• Fixed-Point Unit —Implements all fixed-point instructions, except load/store
• Load/Store Unit —Implements all load and store instructions. No floating-point
instruction prefetch queue, and the interrupt handling mechanism. It controls some data
structures within the register unit.
mechanism, and a history of previous operations to allow for a precise interrupt model.
This module is physically split so that each data structure is implemented near the area
in which it is used.
instructions. This module is subdivided into the following two blocks:
processor load and store instructions are implemented.
IMUL/IDIV–Fixed-point multiply and divide instruction implementation.
ALU/BFU–Fixed-point logic, add, and subtract instruction implementation, as well
as the bit field instructions.
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