mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 806

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
16.10.4.2 IN TOKEN. To guarantee data transfer, the control software must preload the
endpoint FIFO with a data packet prior to receiving an IN token. The software must set up
the endpoint transmit buffer descriptor table and set the STR bit in the USB command
register. The USB controller will fill the transmit FIFO and wait until it receives the IN token.
Once it is received and the FIFO is loaded with the last byte of the data (or at least 4 bytes),
transmission begins.
If data is not ready in the transmit FIFO or if the THS field in the endpoint’s configuration
register is set to respond with NAK, a NAK handshake is returned. If the THS field in the
endpoint’s configuration register is set to respond with STALL, a STALL handshake is
returned. When the end of the current buffer descriptor has been reached and the last buffer
in the packet bit is set, the CRC is appended. Following the transmission of a frame, the USB
controller waits for a handshake packet, depending on the configuration of the endpoint. If
the host fails to acknowledge the packet, the timeout status bit will be set in the buffer
descriptor. It is your responsibility to program the driver software to set the proper
DATA0/DATA1 PID in the transmitted packet.
16.10.4.3 SETUP TOKEN. Setup transactions are similar in format to an OUT token, but
you must use a SETUP rather than an OUT PID. A SETUP token is only recognized by an
endpoint that is configured as a control endpoint. Once the SETUP token is received, setup
data reception begins. The USB controller fetches the next buffer descriptor associated with
the endpoint, and if it is empty, starts transferring the incoming packet to the buffer
descriptor’s associated data buffer. When the data buffer has been filled, the USB controller
clears the E bit in the RX buffer descriptor and generates an interrupt if the I bit in the buffer
descriptor is set. If the incoming packet exceeds the length of the data buffer, the USB
controller fetches the next buffer descriptor in the table and, if it is empty, continues
transferring the rest of the packet to this buffer descriptor’s associated buffer. If it is full, an
error occurs. The entire data packet including the DATA0 PID are written to the receive
buffers. If the packet was received error-free (no CRC errors and no bit stuff error) an ACK
handshake will be transmitted to the host. If a reception error occurred, no handshake
packet will be returned and the error status bits will be set in the last buffer descriptor
associated with this packet.
FIFO LOADED
WITH DATA
Yes
N/A
N/A
N/A
No
Freescale Semiconductor, Inc.
Table 16-33. USB In Token Reception
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
00 (Normal)
00 (Normal)
THS FIELD
11 (STALL)
01 (Ignore)
10 (NAK)
USEP
x
SENT TO HOST
HANDSHAKE
STALL
None
NAK
ACK
NAK
MOTOROLA