mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 445

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

4. Define the UPMB (or UPMA) parameters that control the memory system in the
following sequence. For additional details, see Table 15-11.
— Program the RAM array using the memory command register (MCR) and
— Initialize the option and base registers of the specific bank according to the
— Use the MS field of the option register to select the machine you have chosen
— Program the MBMR to select the number of columns and refresh timer
GPLB4DIS
memory data register (MDR). The RAM word must be written into the MDR
before you issue the WRITE command to the MCR. Repeat this step for all RAM
word entries.
address mapping of the DRAM device you have chosen.
to control the cycles. Notice that the SAM bit in the option register determines
address multiplexing for the first clock cycle and subsequent cycles are
controlled by the UPM RAM words. Also notice that the AMX field in the UPM
RAM word controls the address multiplexing for the next clock cycle rather than
the current cycle.
parameters.
FIELD
WLFB
PTBE
RLFB
AMB
DSB
SAM
PTP
PTB
MS
WP
PS
BI
Freescale Semiconductor, Inc.
REGISTER
For More Information On This Product,
Table 15-11. UPMB Register Settings
MPTPR
MBMR
MBMR
MBMR
MBMR
MBMR
MBMR
MBMR
OR2
OR2
BR2
BR2
BR2
MPC823 REFERENCE MANUAL
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00000010
00001100
VALUE
0011
0011
001
10
00
01
0
1
0
1
0
Selects UPMB
Selects 32-Bit Bus Width
Allows Read and Write Accesses
Prescaler Divided by 32
15.6 s at a 25MHz Clock
Enables Periodic Timer B
Selects Nine Column Address Pins
Selects Two Disable Timer Clock Cycles
Disables the UPWAITB Signal
Selects Three Loop Iterations for Read
Selects Three Loop Iterations for Write
Selects Column Address on First Cycle
Supports Burst Accesses
COMMENTS
Memory Controller
15-89