mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 40

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Number
16-118. SMSYNx Pin Synchronization ................................................................... 16-409
16-119. Time-Slot Assigner Synchronization ......................................................... 16-410
16-120. SPI Block Diagram .................................................................................... 16-431
16-121. SPI Memory Format .................................................................................. 16-439
16-122. SPI Transfer Format If CP is Set to 0........................................................ 16-443
16-123. SPI Transfer Format If CP is Set to 1........................................................ 16-443
16-124. I 2 C Controller Block Diagram.................................................................... 16-453
16-125. I
16-126. Byte Write to Device with Internal Addresses ........................................... 16-456
16-127. Byte Write to Device without Internal Addresses ...................................... 16-456
16-128. Byte Read from Device with Internal Addresses ....................................... 16-457
16-129. Byte Read from Device without Internal Addresses .................................. 16-457
16-130. I
16-131. Parallel Block Diagram For PA15.............................................................. 16-479
16-132. Parallel Block Diagram For PA14.............................................................. 16-480
16-133. MPC823 Interrupt Structure ...................................................................... 16-496
16-134. Interrupt Request Masking ........................................................................ 16-501
17-1.
17-2.
17-3.
17-4.
17-5.
17-6.
17-7.
17-8.
17-9.
17-10. PCMCIA I/O Read of a 16-Bit Slave Port
17-11. PCMCIA I/O Read of an 8-Bit Slave Port
17-12. PCMCIA DMA Read Cycle
18-1.
Figure
(PRS = 0, PSST = 2, PSL = 4, PSHT = 1) .................................................... 17-23
(PRS = 0, PSST = 1, PSL = 3, PSHT = 1) ................................................... 17-22
(PRS = 0, PSST = 1, PSL = 3, PSHT = 0) ................................................... 17-24
(PRS = 2, PSST = 1, PSL = 3, PSHT = 1) ................................................... 17-25
(PRS = 3, PSST = 1, PSL = 4, PSHT = 3) ................................................... 17-26
(PRS = 3, PSST = 1, PSL = 3, PSHT = 0) ................................................... 17-27
(PRS = 3, PSST = 1, PSL = 3, PSHT = 1) ................................................... 17-28
(PPS = 1, PRS = 3, PSST = 1, PSL = 2, PSHT = 0) .................................... 17-29
(PPS = 1, PRS = 3, PSST = 1, PSL = 2, PSHT = 0 ..................................... 17-30
(PRS = 4, PSST = 1, PSL = 3, PSHT = 0) ................................................... 17-31
System with One PCMCIA Socket ................................................................ 17-2
Internal DMA Request Logic ......................................................................... 17-9
PCMCIA Single Beat Read Cycle
PCMCIA Single Beat Read Cycle
PCMCIA Single Beat Read Cycle
PCMCIA Single Beat Write Cycle
PCMCIA Single Beat Write Cycle
PCMCIA Single Beat Write with Wait
PCMCIA Single Beat Read with Wait
LCD Panel ..................................................................................................... 18-2
2
2
C Timing.................................................................................................. 16-455
C Memory Format ................................................................................... 16-464
LIST OF ILLUSTRATIONS (Continued)
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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