mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 361

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Some features are common to all eight memory banks. The full 32-bit decode is available
internally, even if all 32 address bits are not visible outside the MPC823. For external master
transactions, the memory controller extends the 26-bit external address line to 32 bits and
the six most-significant bits are zero. The variable block size of each memory bank can be
between 32K and 64M for a total memory capacity of 512M. Parity can be generated and
checked for any memory bank and each memory bank can be selected for read-only or
read/write operation. For system protection purposes, you can use certain address type
codes to cause the memory controller to restrict access to a memory bank. For additional
flexibility, address type comparisons provide you with a mask option.
The memory controller functionality helps you design MPC823-based systems with little or
no glue logic required. In Figure 15-3, CS0 is used as the 16-bit boot EPROM with the MS
field of the base register 0 configured to select the GPCM. CS1 is used as the RAS signal
for 32-bit DRAM with the MS field of base register 1 configured to select UPMA. The BS_A
signals are used as CASx signals on the DRAM.
MPC823
UPMA
GPCM
Figure 15-3. Simple System Configuration
Freescale Semiconductor, Inc.
For More Information On This Product,
ADDRESS
BS_A[0:3]
GPL1/OE
WE[0:1]
RD/WR
DP[0:3]
DATA
CS0
CS1
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
ADDRESS
CE
OE
WE
DATA
ADDRESS
RAS
CAS[0:3]
W
DATA
PARITY
Memory Controller
EPROM
DRAM
15-5

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