mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 423

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

15.5.5.3 HANDLING VARIABLE ACCESS TIME AND SLOW DEVICES. The memory
controller provides two different mechanisms to interface with slave devices that are either
very slow or cannot guarantee a predefined access time—the wait state and the external TA
signal. These devices can be divided into two main types:
The wait mechanism is used only in accesses that are controlled by the UPM. The
GPLx4DIS bit of the MxMR enables this mechanism. The external TA mechanism is used
only in accesses that are controlled by the GPCM. The SETA bit in the option register
specifies whether TA is generated internally or externally.
15.5.5.3.1 Hierarchical Bus Interface Example. On the local bus, the CPU initiates a
read cycle that addresses the main storage connected to the system bus. The hierarchical
bus interface accepts the local bus request and generates a read cycle on the system bus.
You cannot foresee when the data will be valid to be latched by the CPU, since the system
bus may be occupied by the DMA.
15.5.5.3.2 Slow Device Interface Example. The CPU initiates a read cycle from slow
devices whose access time is greater than the maximum allowed by your programming
model.
• Variable access time devices (FIFO, hierarchical bus interface, dual-port memory
• Slow devices (access time is greater than the maximum allowed by the UPM)
• The Wait Solution—The external module signals to the memory controller that the data
• The External TA Solution—The bus interface module signals to the memory controller
• The Wait Solution—The CPU generates a read access from the slow device. The
• The External TA Solution—The CPU generates a read access from the slow device.
devices)
is not ready by asserting the UPWAITx signal. The memory controller synchronized this
signal because it is an asynchronous signal. As a result of the UPWAITx signal being
asserted, the UPM will enter a freeze mode at the falling edge of the CLKOUT upon
encountering the WAEN bit being set in the UPM word. The UPM will remain in that
state until the UPWAITx signal is asserted. After the negation of UPWAITx, the UPM
will continue executing from the next entry to the end of the pattern (LAST bit is set).
when it can sample the data by asserting the synchronous TA signal.
device will react by asserting the UPWAITx signal as long as the data is not ready. The
CPU will sample the data only after the negation of the UPWAITx signal.
When it is ready, the device is responsible for generating the synchronous TA signal.
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Memory Controller
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