mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 528

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
Restart gate mode performs the same function as normal mode, except it also resets the
counter on the falling edge of the TGATE1 pin. This mode can be used in the following
applications:
The gate function is enabled in the timer mode register and the gate operating mode is
selected in the timer global configuration register.
16.4.2.1 CASCADED MODE. In this mode, the 16-bit timers can be internally cascaded
into a 32-bit counter. Since the decision to cascade timers is made independently, you have
the option of selecting four 16-bit timers or two 32-bit timers. The timer global configuration
register is used to set the timers to cascaded mode, as shown in Figure 16-35.
If the CAS2 bit is set in the timer global configuration register, the two timers function as a
32-bit timer with a 32-bit timer reference register, timer capture register, and timer counter.
In this case, timers 1 and 3 are ignored and timers 2 and 4 must be used to define the mode.
The capture is controlled by the TIN2 pin and the interrupts are generated by the timer event
2 register. When operating in cascaded mode, the cascaded timer reference register, timer
capture register, and timer counter must always be referenced with 32-bit bus cycles.
• Pulse Measurement—The restart gate mode can measure a low pulse on the TGATE1
• Bus Monitoring — The restart gate mode can detect a signal that is abnormally stuck low.
TRR, TCR, TCN CONNECTED TO DATA BUS
PINS 31-16.
TRR, TCR, TCN CONNECTED TO DATA BUS
PINS 31-16.
pin. The rising edge of the TGATE1 pin completes the measurement and if TGATE1 is
externally connected to TINx, it causes the timer to capture the count value and
generate a rising-edge interrupt.
The bus signal must be connected to the TGATE1 pin. The timer count is reset on the
falling edge of the bus signal and if the bus signal does not go high again within the
number of user-defined clocks, an interrupt can be generated.
Note: TGATE1 is internally synchronized to the timebase clock (TMBCLK). If it meets
Figure 16-35. Timer Cascaded Mode Block Diagram
the asynchronous input setup time, then (when working with the internal clock)
the counter begins counting after one system clock.
TIMER1
TIMER3
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
CAPTURE
CAPTURE
Go to: www.freescale.com
TRR, TCR, TCN CONNECTED TO DATA BUS
PINS 15-0.
TRR, TCR, TCN CONNECTED TO DATA BUS
PINS 15-0.
TIMER2
TIMER4
MOTOROLA
CLOCK
CLOCK