mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 216

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
Data Cache
10.4.5 Data Cache Coherency
The MPC823 data cache provides no support for snooping external bus activity. All
coherency between the internal caches and memory/devices external to the extended core
must be controlled by the software. In addition, there is no mechanism provided for DMA or
other internal masters to access the data cache directly.
10.5 DATA CACHE COMMANDS
10.5.1 Flushing and Invalidating the Cache
The MPC823 allows the data cache to be flushed and invalidated when it is being controlled
by the software. The data cache can be invalidated by writing the UNLOCK ALL and
INVALIDATE ALL commands to the DC_CST. The data cache is not automatically
invalidated on reset. It must be invalidated under software control. The data cache can be
flushed by a software loop using the dcbst or dcbf instructions or the implementation-
specific CACHE LINE FLUSH command. Notice that the PowerPC architecture instructions
flush a line indexed by the effective address, while the implementation-specific command
indexes a line by its physical set index within the data cache.
When flushing must be restricted to a specific memory area or the architecture must be
compliant, it is recommended that you use the PowerPC architecture instructions. However,
if the entire data cache must be flushed and there is no concern for compatibility, the
implementation-specific command is more efficient. If a bus error occurs while executing the
dcbf and dcbst instructions or the implementation-specific CACHE LINE FLUSH
command, the data of the cache line specified by these operations must be retrieved from
the copyback data registers rather than from the data cache array.
10.5.2 Enabling and Disabling the Cache
The data cache can be enabled or disabled by writing the DATA CACHE ENABLE and
DATA CACHE DISABLE commands to the DC_CST. In the disabled state, the cache tag
state bits are ignored and all accesses are propagated to the bus as single beat
transactions. The default after the reset state of the data cache is disabled. Disabling the
data cache does not affect the data address translation logic and translation is still controlled
by the MSR
bit. Any write to the DC_CST must be preceded by a sync instruction. This
DR
prevents the data cache from being disabled or enabled in the middle of a data access.
When the data cache generates an interrupt as a result of a bus error on the COPYBACK
or implementation-specific CACHE LINE FLUSH command, it enters the disable state.
Operation of the cache when it is disabled is similar to cache-inhibit operation.
10.5.3 Locking and Unlocking the Cache
Each line of the data cache can be independently locked by writing the LOCK LINE
command to the DC_CST. Replacement line fills are not performed to a locked line. A flush
or invalidation of a locked line cache is ignored by the data cache. Any write to the DC_CST
must be preceded by a sync instruction, which prevents a cache from being locked during
a line fill. Use the UNLOCK LINE or UNLOCK ALL commands to unlock the cache.
MPC823 REFERENCE MANUAL
10-13
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