mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 700

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
RXDx
HDLC SCCE
Communication Processor Module
HDLC SCCE
CDx
NOTES:
TXDx
RTSx
CTSx
NOTES:
1. RXB event assumes receive buffers are 6 bytes each.
2. The second IDL event occurs after 15 ones are received in a row.
3. The FLG interrupts show the beginning and end of flag reception.
4. The FLG interrupt at the end of the frame may precede the RXF interrupt due to receive FIFO latency.
5. The CDx event must be programmed in the port C parallel I/O, not in the SCC itself.
6. F is set to flag, A is set to address byte, C is set to control byte, I is set to information byte, and CR is set to CRC byte.
EVENTS
EVENTS
1. TXB event shown assumes all three bytes were put into a single buffer.
2. Example shows one additional opening flag. This is programmable.
3. The CTSx event must be programmed in the port C parallel I/O, not in the SCC itself.
TRANSMITTED BY HDLC
RECEIVED IN HDLC
TIME
FRAME
FRAME
LINE IDLE
CDx
LINE IDLE
Figure 16-79. HDLC Interrupt Event Example
IDL
Freescale Semiconductor, Inc.
F
FLG
For More Information On This Product,
F
A
CTSx
FLG
STORED IN RX BUFFER
A
MPC823 REFERENCE MANUAL
F
C
Go to: www.freescale.com
F
I
STORED IN
TX BUFFER
A
I
A C CR CR F
I
RXB
CR CR
F
RXF
FLG
TXB
FLG
IDL
LINE IDLE
CTSx
LINE IDLE
CDx
MOTOROLA

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