mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 159

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
The PowerPC Core
6.6.7 Little-Endian Mode Support
The load/store unit implements the little-endian mode as it is specified by the PowerPC
architecture and in this mode the modified address is issued to the data cache. For an
individual scalar unaligned transfer or an attempted execution of a multiple/string instruction,
an alignment exception is generated.
6.6.8 Atomic Update Primitives
The lwarx and stwcx instructions are atomic update primitives. Storage reservation
accesses made by the same processor are implemented by the load/store unit. The external
bus interface module implements storage reservation as it relates to accesses made by
external bus masters. Accesses made by other internal masters to internal memories
implements storage reservation as it relates to special internal bus snoop logic. This logic is
implemented in the data cache.
When a lwarx instruction is executed the load/store unit issues a cycle to the data cache
with a special attribute. For an external memory access, this attribute causes the external
bus interface module to set a storage reservation on the cycle address. The external bus
interface module is then responsible for snooping the external bus or getting an indication
from external snoop logic if the storage reservation is broken by some other processor
accessing the same location. When an stwcx instruction to external memory is executed,
the external bus interface module checks to see if a reservation was lost. If loss of
reservation has occurred, the cycle is blocked from going to the external bus and the
external bus interface module notifies the load/store unit of a stwcx failure.
The MPC823 storage reservation supplies hooks for the support of storage reservation
implementation in a hierarchical bus structure. For a full description of the storage
reservation mechanism, refer to Section 7 PowerPC Architecture Compliance. In case
of storage reservation on internal memory, a lwarx indication causes the on-chip snoop
logic to latch the address. This logic notifies the load/store unit in the case of an internal
master store access, then the reservation is reset. If a new lwarx instruction address phase
is successfully executed it replaces any previous storage reservation address at the
appropriate snoop logic. However, when an stwcx instruction is executed, the storage
reservation is canceled, unless an alignment interrupt condition is detected.
MPC823 REFERENCE MANUAL
6-29
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