mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 735

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

16.9.19.12.5 Differences Between HDLC and ASYNC HDLC. There are four main
differences between the HDLC and ASYNC HDLC modes of operation:
16.9.19.12.6 SCCx ASYNC HDLC Programming Guide. The following is an initialization
sequence guide for a serial communication controller in asynchronous HDLC mode.
• There is no maximum received frame length counter in the ASYNC HDLC controller.
• If an error prevents a frame from being received, the character received at the moment
• The automatic error counters in HDLC mode have not been implemented in
• Noisy characters (those whose three samples are not the same) are not accounted for
1. Initialize the SDCR.
2. In NMSI mode, configure the port A pins to enable RXDx and TXDx.
3. Configure a baud rate generator to generate appropriate channel clocking frequency.
4. Program the SICR to route the baud rate generator clocking to a serial communication
5. Select whether the channel is using the time-slot assigner or the NMSI pins in the
6. Write RBASE and TBASE in the SCCx parameter RAM to point to the first RX and TX
7. Issue the INIT RX AND TX PARAMS command for the serial communication
8. Program the RFCR and TFCR.
9. Write the MRBLR with the maximum receiver buffer size.
10. Write C_MASK and C_PRES with the standard values.
11. Write the ZERO register to 0x0000.
12. Program the RFTHR to the number of frames that must be received before an interrupt
Therefore, the controller receives all characters between opening and closing flags and
there is no way to stop the controller from writing to memory. This in no way affects the
number of bytes received into a specific buffer descriptor. It just means that a frame is
received into memory in its entirety.
the error occurred is not written into memory. For example, if a CD lost error occurred,
the frame is closed and the partial character is not written to memory. Thus, the octet
count only reflects the number of bytes written to memory.
asynchronous HDLC mode.
in the ASYNC HDLC controller. It is assumed that the CRC catches any data integrity
problems.
controller that is in asynchronous HDLC mode.
SICR.
buffer descriptor.
controller.
is generated.
Note: The GRACEFUL STOP TRANSMIT command is not supported by the ASYNC
HDLC controller.
Freescale Semiconductor, Inc.
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MPC823 REFERENCE MANUAL
Go to: www.freescale.com
Communication Processor Module
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