mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 537

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

16.5.2 The SDMA Registers
The SDMA channels share a configuration register, address register, and status register.
They are all controlled by the configuration of the serial communication controllers, serial
management controllers, serial peripheral interface, and I
16.5.2.1 SDMA CONFIGURATION REGISTER. The 32-bit SDMA configuration register
(SDCR) is used to configure all 16 SDMA channels. It is always read/write in supervisor
mode, even though writing to the SDCR is not recommended unless the communication
processor module is disabled. The control provided by this register has interactions with the
DMA controllers in the LCD and video controller modules of the MPC823. Refer to
Section 18.3.6 DMA Control and Section 18.3.1 FIFO Control for more information
regarding those modules.
Bits 0–16—Reserved
These bits are reserved and must be set to 0.
FRZ—Freeze
This field determines the action to be taken when the FRZ signal is asserted. The SDMA
negates the BR signal and keeps it that way until FRZ is negated or a reset occurs.
SDCR
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
00 = The SDMA channels ignore the FRZ signal.
01 = Reserved.
10 = The SDMA channels freeze on the next bus cycle.
11 = Reserved.
RES
16
R
0
0
17
1
FRZ
R
0
18
2
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RESERVED
21
5
(IMMR & 0xFFFF0000) + 0x030
(IMMR & 0xFFFF0000) + 0x030
R
0
22
6
RESERVED
23
7
R
0
24
8
LAM RESERVED
R/W
25
9
0
2
C controller.
Communication Processor Module
10
26
R
0
11
27
12
28
LAID
R
0
13
29
14
30
RAID
R
0
16-85
15
31