mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 910

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Freescale Semiconductor, Inc.
Communication Processor Module
When communicating to either slave device, set the R bit in the TX buffer descriptor to
prepare it for transmission. Set the I bit in the TX and RX buffer descriptors to enable the
2
transmission and reception status to be updated in the I2CE register and to enable I
C
interrupts to the core. Set the E bit on the RX buffer descriptor to prepare it for reception.
Finally, set the STR bit in the I2COM register to initiate transmission. The data starts
2
transmitting once the SDMA channel loads the transmit FIFO with data and the I
C bus is
not busy.
2
2
16.13.3.1.3 I
C Loopback Configuration. Loopback on the I
C controller is a special part
of master mode operation with a device that does not contain internal addresses. Refer to
Figure 16-127 for more information. To begin a loopback transmission, you must prepare a
TX buffer descriptor with a data buffer N+1 bytes long, where N is the number of data bytes
2
to be written back to the I
C controller. You must also prepare one or more RX buffer
descriptors to receive the N bytes of data.
2
The first byte of the TX buffer descriptor must contain the address of the MPC823 I
C
device’s own address, which is in the I2CADD register, followed by the write bit asserted (R/
W = 0). The remaining N bytes of the TX buffer descriptor contain the data to be sent and
2
received by the I
C controller.
Next, set the R bit in the TX buffer descriptor and the E bit in the RX buffer descriptor. Then
set the W and L bits in the TX buffer descriptor. Setting the L bit causes a stop condition to
be issued after this buffer is transmitted to conclude the operation. Set the I bit in the TX and
RX buffer descriptors to enable the transmission and reception status to be updated in the
2
I2CE register and to enable I
C transmit and receive interrupts to the core. You must then
set the STR bit in the I2COM register to initiate the loopback operation.
2
2
16.13.3.2 I
C SLAVE MODE. When the I
C controller is in slave mode, it receives
2
2
messages from an I
C master and sends back a reply. Once the I
C controller is configured
for slave mode operation (by clearing the M/S bit in the I2COM register), the SCL signal
2
becomes an input driven by the external master. The I
C controller can operate with an SCL
of any frequency from DC to 400kHz or more.
2
After the start condition, the first transmitted byte to the I
C slave device contains the 7-bit
2
slave device address and the read/write bit. The I
C controller will compare the transmitted
slave device address with its own programmed address. If there is a match, the read/write
bit is evaluated.
You must the clear the M/S bit in the I2COM register to configure the controller as a slave.
You do not program the I2MOD and I2BRG registers to set the SCL frequency, as SCL is
2
an input to the slave. Instead, program the I2ADD register with the 7-bit I
C address of the
2
slave. Enable the I
C controller by setting the EN bit in the I2MOD register.
MPC823 REFERENCE MANUAL
MOTOROLA
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