mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1046

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Video Controller
BR—Blanking on Rising Edge of the Clock
BF—Blanking on Falling Edge of the Clock
Bits 8–13 and 17–18—Reserved
These bits are reserved and must be set to 0.
VDS—Video Data Select
This field selects the source of the video data or holds the last value of the data for the next
CNT cycle.
INT—Interrupt
0 = The value of the BLANK signal will be 0 after the rising edge of the clock.
1 = The value of the BLANK signal will be 1 after the rising edge of the clock.
0 = The value of the BLANK signal will be 0 after the falling edge of the clock.
1 = The value of the BLANK signal will be 1 after the falling edge of the clock.
00 = Select active video from display frame buffer (FIFO output).
01 = Select inactive (background) video from the background color buffer.
10 = Hold last value of data.
11 = Reserved.
0 = Do not generate a interrupt to the core.
1 = Generate a maskable interrupt (end of frame) after this entry completes and before
the next one begins.
Note: All pins are general-purpose and can be programmed according to your
requirements. The signal pin value only changes at the first cycle in which the
line is valid. If a line is valid for more than one clock (CNT > 1), the signal holds
its last assigned value.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
MOTOROLA

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