mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 278

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

LVM—Level Mask 0–7
When set, these bits enable a LEVELx interrupt request from an internal source to be
generated. The SIPEND register contains the corresponding LVLx bits. See Figure 12-2 for
more information.
Bits 16–31—Reserved
These bits are reserved and must be set to 0.
12.3.3.3 SIU INTERRUPT EDGE/LEVEL REGISTER. The 32-bit read/write SIU interrupt
edge/level (SIEL) register contains pairs of bits that correspond to an external interrupt
request. If set, the EDx bit specifies when a falling edge in the corresponding IRQx signal is
an interrupt request. When the EDx bit is 0, a low logical level in the IRQx signal is an
interrupt request. The WMx bit, if set, indicates that a low level detection in the
corresponding interrupt request line causes the MPC823 to exit low-power mode.
ED—Edge Detect 0–7
WM—Wake-Up Mask 0–7
SIEL
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
0 = Disable the generation of an IRQx bit in the SIPEND register.
1= Enable the generation of an IRQx bit in the SIPEND register.
0 = The bits specify that a low logical level in the IRQx signal is detected as an interrupt
1 = The bits specify that a falling edge in the corresponding IRQx signal is detected as
0 = Not allowed to exit from low-power mode.
1 = Allows low-level detection in the corresponding IRQx signal to exit or wake up the
request.
an interrupt request.
MPC823 from low-power mode.
ED0 WM0 ED1 WM1 ED2 WM2 ED3 WM3 ED4 WM4 ED5 WM5 ED6 WM6 ED7 WM7
R/W
16
0
0
R/W
17
1
0
R/W
18
2
0
Freescale Semiconductor, Inc.
R/W
For More Information On This Product,
19
3
0
R/W
20
MPC823 REFERENCE MANUAL
4
0
Go to: www.freescale.com
R/W
21
5
0
(IMMR & 0xFFFF0000) + 0x018
(IMMR & 0xFFFF0000) + 0x018
R/W
22
6
0
RESERVED
R/W
23
7
0
R/W
0
R/W
24
8
0
R/W
25
9
0
R/W
10
26
0
R/W
11
27
0
R/W
System Interface Unit
12
28
0
R/W
13
29
0
R/W
14
30
0
R/W
12-9
15
31
0