mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 172

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

7.3.7.3.6 Program Interrupt. The MPC823 cannot generate a floating-point exception type
interrupt. Likewise, an illegal instruction type program interrupt is not generated by the core,
but an implementation-dependent software emulation interrupt is generated instead. A
privileged instruction program interrupt is generated for an on-core valid special-purpose
register (SPR) field or any SPR encoded as an external special register if SPR
MSR
See Table 6-11 for details.
7.3.7.3.7 Floating-Point Unavailable Interrupt. The MPC823 cannot generate a
floating-point exception type interrupt. An implementation-dependent software emulation
interrupt will be taken when you try to execute floating-point instruction, regardless of
MSR
7.3.7.3.8 Trace Interrupt. A trace interrupt occurs if MSR
rfi is successfully completed or if MSR
interrupt does not occur after an instruction that causes an interrupt. The monitor/debugger
software must change the vectors of other possible interrupt addresses to single-step these
instructions. If this is unacceptable, other debug features can be used. Refer to
Section 20 Development Capabilities and Interface for more information. The following
registers are set on a trace interrupt:
SRR0—Save/Restore Register 0
Set to the effective address of the instruction following the executed instruction.
SRR1—Save/Restore Register 1
MSR—Machine State Register
Execution resumes at offset x’00D00’ from the base address indicated by MSR
7.3.7.3.9 Floating-Point Assist Interrupt. The floating-point assist interrupt is not
generated by the MPC823. An implementation-dependent software emulation interrupt will
be taken when you try to execute a floating-point instruction.
1–4
10–15
Other
IP
ME
LE
Other
PR
FP
.
=1, as well as if you try to execute privileged instruction occurred when MSR
Set to 0.
Set to 0.
Loaded from bits 16-31 of the MSR. In the current implementation, Bit 30 of
the SRR1 is never cleared, except by loading a zero value from MSR
No change.
No change.
Bits are copied from the ILE.
Set to 0.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
BE
= 1 and a branch is completed. Notice that the trace
SE
PowerPC Architecture Compliance
= 1 and any instruction except
0
IP
=1 and
.
RI
PR
.
=1.
7-11