mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 198

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Instruction Cache
9.4.2 Loading and Locking the Instruction Cache
The LOAD & LOCK command is used to lock critical code segments in the instruction
cache. This operation is privileged and any attempt to perform it when the core is in the
problem state (MSR
cache line granularity and after a line is locked, it operates as a regular instruction SRAM. It
is not replaced during misses and it is not affected by invalidation commands. The hardware
operation trusts the software to follow the exact steps mentioned in Section 9.7 Updating
Code And Memory Region Attributes . To load and lock a line, follow these steps:
After the LOAD & LOCK command is written to the IC_CST, the cache checks to see if the
line containing the byte addressed by the IC_ADR is in the cache. If it is a hit, the line is
locked and the command terminates with no exception. If it is not, a regular miss sequence
is initiated. After the whole line is placed in the cache, the line is locked. You must check the
error type bits in the IC_CST to determine if the LOAD & LOCK operation completed
properly. The LOAD & LOCK command can generate two errors:
9.4.3 Unlocking A Line
The UNLOCK LINE command is used to unlock previously locked cache lines. This
operation is privileged and any attempt to perform it when the core is in the problem state
(MSR
granularity. If the line is found in the cache it is considered a hit, thus it is unlocked and
operates as a regular valid cache line. If the line is not found in the cache it is considered a
miss, there is no operation and the command terminates without an exception. To unlock a
line, follow these steps:
This command has no error cases that you need to check. The instruction cache performs
this instruction in one clock cycle. To accurately calculate the latency of this instruction, bus
latency must be taken into consideration.
1. Read the error type bits in the IC_CST to clear them.
2. Write the address of the line to be locked to the IC_ADR.
3. Set the LOAD & LOCK command in the IC_CST.
4. Execute the isync instruction.
5. Return to Step 2 to load and lock more lines.
6. Read the error type bits in the IC_CST to determine if the operation completed
• Type 1—A bus error occurs in one of the cycles that fetched the line.
• Type 2—There is no place to lock. It is your responsibility to make sure that there is at
1. Write the address of the line to be unlocked into the IC_ADR.
2. Set the UNLOCK LINE command in the IC_CST.
least one unlocked way in the appropriate set.
properly.
PR
= 1) results in a program interrupt. UNLOCK LINE is performed on a cache line
PR
= 1) results in a program interrupt. LOAD & LOCK is performed on a
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