mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1268

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

rfi
Definition
Operation
Description
FIELD
FIELD
BIT
BIT
16
0
17
1
00000
18
2
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19
For More Information On This Product,
19
3
NIA
the MSR. If the new MSR value does not enable any pending
exceptions, then the next instruction is fetched, under control of
the new MSR value, from the address SRR0[0–29] || 0b00. If the
new MSR value enables one or more pending exceptions, the
exception associated with the highest priority pending exception
is generated; in this case the value placed into SRR0 by the
exception processing mechanism is the address of the
instruction that would have been executed next had the
exception not occurred. Note that an implementation may define
addtional MSR bits, and in this case, may also cause them to be
saved to SRR1 from MSR on an exception and restored to MSR
from SRR1 on an rfi. This is a supervisor-level, context
synchronizing instruction.
Other registers altered:
Return from Interrupt
MSR[16–23, 25–27, 30–31]
Bits SRR1[0,5-9,16-31] are placed into the corresponding bits of
POWERPC ARCHITECTURE
20
MPC823 REFERENCE MANUAL
4
iea SRR0[0–29] || 0b00
MSR
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21
5
LEVEL
OEA
22
6
23
7
00000
24
8
25
9
SUPERVISOR
SRR1[16–23, 25–27, 30–31]
50
LEVEL
10
26
MPC823 Instruction Set—rfi
11
27
OPTIONAL
12
28
00000
13
29
14
30
FORM
XL
B-115
15
31
0