mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1112

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

LBRK—Load/Store Breakpoint Interrupt
This bit is set as a result of the assertion of an load/store breakpoint. The core enters debug
mode if enabled and the LBRKE bit in the DER is set.
IBRK—Instruction Breakpoint Interrupt
This bit is set as a result of the assertion of an instruction breakpoint. The core enters debug
mode if enabled and the IBRKE bit in the DER is set.
EBRK—External Breakpoint Interrupt
This bit is set as a result of the assertion of an external breakpoint. The core enters debug
mode if enabled and the EBRKE bit in the DER is set.
DPI—Development Port Interrupt
This bit is set by the development port as a result of a debug station nonmaskable request
or when entering debug mode immediately out of reset. The core enters debug mode if
enabled and the DPIE bit in the DER is set.
20.6.3.2 DEBUG ENABLE REGISTER. The debug enable register (DER) allows the
enabling of events that cause the processor to enter debug mode.
DER
Bits 0, 4, and 5—Reserved
These bits are reserved and must be set to 0.
RSTE—Reset Interrupt Enable
RESET
RESET
FIELD
FIELD
R/W
SPR
R/W
SPR
BIT
BIT
0 = Debug mode entry is disabled (reset value).
1 = Debug mode entry is enabled.
RES
R/W
RES
R/W
16
0
0
0
RSTE
SEIE
R/W
R/W
17
1
0
0
ITLBMS
CHSTP
R/W
R/W
18
2
E
1
E
0
Freescale Semiconductor, Inc.
DTLBM
MCIE
For More Information On This Product,
R/W
R/W
19
SE
3
0
0
ITLBERE
R/W
20
MPC823 REFERENCE MANUAL
4
0
RESERVED
R/W
Go to: www.freescale.com
0
DTLBER
R/W
21
5
E
0
EXTIE
R/W
22
6
0
ALIE
R/W
23
7
0
149
149
PRIE
R/W
24
8
RESERVED
0
R/W
0
Development Capabilities and Interface
FPUVI
R/W
25
9
E
0
DECIE
R/W
10
26
0
11
27
RESERVED
R/W
0
LBRKE
R/W
12
28
1
SYSIE
IBRKE
R/W
R/W
13
29
0
1
EBRKE
TRE
R/W
R/W
14
30
1
1
20-57
DPIE
RES
R/W
R/W
15
31
0
1