mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 729

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

16.9.19.12.2 SCCx ASYNC HDLC Receive Buffer Descriptor. The SCCx ASYNC HDLC
controller uses the receive (RX) buffer descriptor to report information about each buffer’s
received data. An example of the RX buffer descriptor process is illustrated in Figure 16-78.
The first word of the RX buffer descriptor contains control and status bits. Bit 0 is set by the
core when the buffer is available to the SCCx ASYNC HDLC controller and it is cleared by
the controller when the buffer is full.
E—Empty
Bits 1, 7, and 10–11—Reserved
These bits are reserved and must be set to 0.
W—Wrap (Final Buffer Descriptor in Table)
NOTE:
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
0 = The data buffer associated with this buffer descriptor is filled with data or stops
1 = The data buffer associated with this buffer descriptor is empty or currently receiving
0 = This is not the last buffer descriptor in the RX buffer descriptor table.
1 = This is the last buffer descriptor in the RX buffer descriptor table. After this buffer
You are only responsible for initializing the items in bold.
receiving because an error condition occurred. The core is free to examine or write
to any fields of this RX buffer descriptor. The communication processor module
does not use this buffer descriptor again as long as the E bit is zero.
data. This RX buffer descriptor and its associated receive buffer are owned by the
communication processor module. Once the E bit is set, the core must not write
any fields of this RX buffer descriptor.
is used, the communication processor module receives incoming data into the first
buffer descriptor that RBASE points to in the table. The number of RX buffer
descriptors in this table are programmable and determined only by the W bit and
overall space constraints of the dual-port RAM.
0
E
Note: The communication processor module sets all the status bits in this buffer
RES
1
W
descriptor, but you must clear them before submitting the buffer descriptor to the
communication processor module.
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Freescale Semiconductor, Inc.
For More Information On This Product,
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MPC823 REFERENCE MANUAL
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Go to: www.freescale.com
F
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RX DATA BUFFER POINTER
CM
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DATA LENGTH
RES BRK BOF
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8
9
Communication Processor Module
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RES
11
AB
12
CR
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OV
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16-277
CD
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