mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 894

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
PM—Prescale Modulus Select
This field specifies the divide ratio of the prescale divider in the SPI clock generator. The
BRGCLK is divided by 4 * ([PM0–PM3] + 1), thus giving a clock divide ratio of 4 to 64. The
clock has a 50% duty cycle.
16.12.4.1.1 SPI Examples With Different LEN Values. The programming examples
below illustrate the effect of the LEN field and the REV bit in the SPMODE register on output
from the SPI controller. They illustrate the master mode output from the SPI controller as the
LEN varies. To help map the output process, make g through v the binary symbols, use x to
indicate a deleted bit, use __ to indicate original byte boundaries, and use _ to indicate
original nibble (4-bit) boundaries.
The initial pattern for all examples is ghij_klmn__opqr_stuv.
Example 1
Data Selected:
Data Transmitted for REV=0:
Data Transmitted for REV=1:
Example 2
Data Selected:
Data Transmitted for REV=0:
Data Transmitted for REV=1:
Example 3
Data Selected:
Data Transmitted for REV=0:
Data Transmitted for REV=1:
Example 4
Data Selected:
Data Transmitted for REV=0:
Data Transmitted for REV=1:
LEN = 0x4
LEN = 0x7
LEN = 0xc
LEN = 0xf
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
(Data Size = 5)
(Data Size = 8)
(Data Size = 13)
(Data Size = 16)
xxxj_klmn_xxxr_stuv
nmlk_j__vuts_r
j_nmlk__r_stuv
ghij_klmn_opqr_stuv
nmlk_jihg__vuts_rqpo
ghij_klmn__opqr_stuv
ghij_klmn_xxxr_stuv
nmlk_jihg__vuts_r
r_stuv__ghij_klmn
ghij_klmn_opqr_stuv
nmlk_jihg__vuts_rqpo
opqr_stuv__ghij_klmn
MOTOROLA