mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 958

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
In a polled interrupt scheme, you must periodically read the CIPR. When a pending interrupt
is handled, clear the corresponding bit in the CIPR. However, if an event register exists,
clear the unmasked event register bits instead, thus causing the CIPR bit to be cleared. To
clear a bit in the CIPR, write a 1 to that bit. Since you can only clear bits in this register, bits
written as zeros are unaffected. The CIPR is cleared at reset.
16.15.5.3 CPM INTERRUPT MASK REGISTER. Each bit in the 32-bit read/write CPM
interrupt mask register (CIMR) corresponds to a CPM interrupt source. You can mask an
interrupt by clearing the corresponding bit in the CIMR and you can enable one by setting
the corresponding bit in the CIMR. When a masked CPM interrupt occurs, the corresponding
bit in the CIPR is still set, regardless of the CIMR bit, but no interrupt request is passed to
the core.
If a CPM interrupt source is requesting interrupt service when you clear its corresponding
bit in the CIMR, the request stops. If you set its bit in the CIMR later, a previously pending
interrupt request is processed by the core, according to its assigned priority. You can read
the CIMR at any time and it is cleared by reset.
CIMR
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
PC15
PC11
R/W
R/W
16
0
0
0
Note: The USB or SCCx CIPR bit positions are not changed according to the relative
PC10
USB
R/W
R/W
17
1
0
0
priority between the USB or SCCs (as determined by the SCxP and SPS bits in
the CICR). Writing a zero to a bit in the CIPR has no effect.
SCC2
RES
R/W
R/W
18
2
0
0
Freescale Semiconductor, Inc.
TIMER
SCC3
For More Information On This Product,
R/W
R/W
19
3
0
3
0
RES
R/W
PC9
R/W
20
MPC823 REFERENCE MANUAL
4
0
0
Go to: www.freescale.com
PC14
R/W
PC8
R/W
21
5
0
0
TIMER
R/W
PC7
R/W
22
6
1
0
0
(IMMR & 0xFFFF0000) + 0x948
(IMMR & 0xFFFF0000) + 0x94A
PC13
RES
R/W
R/W
23
7
0
0
TIMER
PC12
R/W
R/W
24
8
0
4
0
SDMA
R/W
PC6
R/W
25
9
0
0
IDMA1
R/W
R/W
10
26
SPI
0
0
IDMA2
SMC1
R/W
R/W
11
27
0
0
SMC2
RES
R/W
R/W
12
28
0
0
TIMER
R/W
PC5
R/W
13
29
2
0
0
MOTOROLA
R–TT
R/W
PC4
R/W
14
30
0
0
RES
R/W
R/W
15
31
I2C
0
0