mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 846

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
16.11.6.8 SENDING A PREAMBLE. A preamble sequence provides a convenient way for
you to ensure that the line is idle before you start a new message. The preamble sequence
is constructed of consecutive ones that are one character long. If the preamble bit in a buffer
descriptor is set, a serial management controller sends a preamble sequence before
transmitting that data buffer. For 8 data bits, no parity, 1 stop bit, and 1 start bit, a preamble
of 10 ones would be sent before the first character in the buffer. If no preamble sequence is
sent, data from two ready transmit buffers can be transmitted without causing a delay on the
transmit pin between the two transmit buffers.
16.11.6.9 SMCx UART CONTROLLER ERRORS. The SMCx UART controller reports
character reception error conditions via the channel buffer descriptors and the SMCx UART
event register. The SMCx UART controller has no transmission errors, which means you
cannot stop the transmission of characters in SMCx UART mode.
• Overrun Error—The SMCx UART controller maintains a two-character length FIFO for
• Parity Error—When this error occurs, the channel writes the received character to the
• Idle Sequence Receive Error—An idle is detected when one character consisting of all
• Framing Error—The SMCx UART controller receives this error when it receives a
• Break Sequence Error—This error occurs when the SMCx UART receiver receives an
receiving data. The data is moved to the buffer after the first character is received into
the FIFO and if a receiver FIFO overrun occurs, the channel writes the received
character into the internal FIFO. Then the channel writes the received character to the
buffer, closes it, sets the OV bit in the receive buffer descriptor, and generates a receive
interrupt if it is enabled. Reception then continues as normal.
buffer, closes it, sets the PR bit in the buffer descriptor, and generates the receive
interrupt if it is enabled. Reception then continues as normal.
ones is received. Once an idle is received, the channel counts the number of
consecutive idle characters. If the count reaches the MAX_IDL value, the buffer is
closed, and an receive interrupt is generated. If no receive buffer is open, this event
does not generate an interrupt or any status information. The idle counter is reset every
time a character is received.
character with no stop bit. When this error occurs, the channel writes the received
character to the buffer, closes the buffer, sets the FR bit in the buffer descriptor, and
generates the receive interrupt if it is enabled. When this error occurs, parity is not
checked for the character.
all-zero character with a framing error. When it occurs, the channel increments the
BRKEC entry and generates a maskable BRK interrupt in the SMCE–UART register.
The channel also measures the length of the break sequence and stores this value in
the BRKLN counter. If the channel was in the middle of buffer processing when the
break was received, the buffer is closed with the BR bit in the receive buffer descriptor
set and the receive interrupt is generated if it is enabled.
Note: The SMCx UART controller may occasionally get an overrun error when the line
is idle, in which case, ignore the error.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
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