mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 564

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
16.6.3.16 BUS EXCEPTIONS. When IDMA has the bus and is performing operand
transfers, bus exceptions can occur. When a synchronous bus structure like those
supported by the MPC823 is used, you can make provisions that allow a bus master to
detect and respond to errors during a bus cycle. IDMA recognizes the same bus exceptions
that the core recognizes at reset or when a transfer error occurs.
16.7 THE SERIAL INTERFACE WITH TIME-SLOT ASSIGNER
The serial interface connects the physical layer serial lines to the serial communication
controllers (SCCs) and two serial management controllers (SMCs). In its simplest
configuration, the serial interface allows these controllers to be connected to their own set
of individual pins. The serial communication controller or serial management controller that
connects to the external world in this way connects to a nonmultiplexed serial interface
(NMSI). In an NMSI configuration, the serial interface provides a flexible clocking
assignment for the serial communication controller or serial management controller from a
bank of external clock pins and/or internal baud rate generators.
However, the main feature of the serial interface is its time-slot assigner (TSA), which allows
any combination of the serial communication or management controllers to multiplex their
data together on one time-division multiplexed (TDMA) channel. Common examples of
TDMs are the T1 lines in the U.S. or Japan and the CEPT lines in Europe. Even if the
time-slot assigner is not used in its intended capacity, it can still be used to generate
complex waveforms on eight output pins (L1ST[1:8]). For example, these pins can be
programmed by the time-slot assigner to implement stepper motor control or variable duty
cycle and period control on these pins. Any programmed configuration can be changed
on-the-fly. The serial interface block diagram is illustrated in Figure 16-43.
• Reset—On an external reset, IDMA immediately aborts channel operation, returns to
• Transfer error—When a fatal error occurs during a bus cycle, a bus error exception is
the idle state, and clears the IDSRx. If a bus cycle is in progress when reset is detected,
the cycle is terminated, the control and address/data pins are three-stated, and bus
ownership is released.
used to abort the cycle and systematically terminate that channel operation. The IDMA
terminates the current bus cycle, signals an error in the SDSR, and signals an interrupt
if the corresponding bit in the SDMR is set. IDMA waits for the RISC microcontroller to
reset before starting any new bus cycles. It must be noted that any data previously read
from the source into the internal storage is lost.
Note: Any device that is the source or destination of the operand under IDMA
handshake control for single address transfers may need to monitor TEA to
detect a bus exception for the current bus cycle. TEA terminates the cycle
immediately and negates SDACKx, which is used to control the transfer to or
from the device.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
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