mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1158

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

The table below describes instruction field notation conventions used in this appendix.
CONVENTION
NOTATION/
Undefined
SPR(x)
Rotate
TRAP
UISA
OEA
Shift
VEA
NIA
Set
THE ARCHITECTURE
Next instruction address, which is the 32-bit address of the next instruction to be executed
(the branch destination) after a successful branch. In pseudocode, a successful branch is
indicated by assigning a value to NIA. For instructions which do not branch, the next
instruction address is CIA + 4. Does not correspond to any architected register.
PowerPC operating environment architecture
Rotate the contents of a register right or left n bits without masking. This operation is used
for rotate and shift instructions.
Bits are set to 1.
Shift the contents of a register right or left n bits, clearing vacated bits (logical shift). This
operation is used for rotate and shift instructions.
Special-purpose register x
Invoke the system trap handler.
An undefined value. The value may vary from one implementation to another, and from
one execution to another on the same implementation.
PowerPC user instruction set architecture
PowerPC virtual environment architecture
Freescale Semiconductor, Inc.
SPECIFICATION
RA, RB, RT, RS
For More Information On This Product,
BA, BB, BT
/, //, ///
FXM
DS
SI
UI
D
U
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
crb A, crb B, crb D (respectively)
r A, r B, r D, r S (respectively)
DEFINITION
EQUIVALENT
0...0 (shaded)
SIMM
UIMM
CRM
IMM
ds
d
MPC823 Instruction Set
B-5