mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 139

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

In the event of an exception, the machine state necessary to recover the architectural state
is available. As instructions finish executing, they are released (retired) from the queue and
the buffer storage is reclaimed for new instructions entering the queue. An exception can be
detected at any time during instruction execution and is recorded in the history buffer when
the instruction finishes execution. The exception is not recognized until the faulting
instruction reaches the head of the history queue, but once the exception is recognized, an
interrupt process begins. The queue is reversed and the machine is restored to its state at
the time the instruction is issued. Machine state is restored at a maximum rate of two
floating-point and two fixed-point instructions per clock.
To correctly restore the architectural state, the history buffer must record the value of the
destination before the instruction is executed. The destination of a store instruction,
however, is in memory and it is not practical from a performance standpoint to always read
memory before writing it. Therefore, stores issue immediately to store buffers, but do not
update memory until all previous instructions have finished executing without exception or
the store has reached the head of the history buffer.
The history buffer has enough storage to hold the state of six instructions, but no more than
four fixed-point instructions. The other two instructions can be condition code or branch
instructions. In the event of a long latency instruction, it is possible that issued instructions
will fill the history buffer. If so, instruction issue waits until the long latency operation finishes.
The following types of instructions can potentially cause the history buffer to fill:
• Floating-point arithmetic instructions
• Integer divide instructions
• Instructions that affect or use resources external to the core (load/store instructions)
INSTRUCTIONS
ISSUED
Freescale Semiconductor, Inc.
QUEUE
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TAIL
Figure 6-5. History Buffer Queue
MPC823 REFERENCE MANUAL
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HISTORY BUFFER QUEUE
COMPLETED INSTRUCTIONS
WRITEBACK
QUEUE
HEAD
The PowerPC Core
INSTRUCTIONS
RETIRED
6-9